SPECTROMETERS CURRENTLY EMPLOYED BY NASA INCLUDE FIELD PROGRAMMABLE ARRAYS (FPGAS), ANALOG TO DIGITAL CONVE…

Public award description

SPECTROMETERS CURRENTLY EMPLOYED BY NASA INCLUDE FIELD PROGRAMMABLE ARRAYS (FPGAS), ANALOG TO DIGITAL CONVERTERS (ADCS) AND A NUMBER OF OTHER DISCRETE COMPONENTS ASSEMBLED ON A PRINTED CIRCUIT BOARD (PCB). AN APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) BASED SPECTROMETER OFFERS A GREAT REDUCTION IN WEIGHT, VOLUME AND POWER CONSUMPTION COMPARED TO THE FPGA/PCB BASED IMPLEMENTATION. THIS PROPOSAL AIMS TO DEVELOP A LOW-POWER (LP) POLY-PHASE SPECTROMETER (PPS) ASIC. THE PROPOSED ASIC AIMS TO ACHIEVE A 4GHZ BANDWIDTH AND 8192 USABLE FREQUENCY BINS. IN ORDER TO IMPLEMENT THE REQUIRED FUNCTIONALITY AND MEET THE SPECIFICATIONS WHILE CONSUMING BELOW 1.5W OF POWER, THE PROPOSED ASIC WILL INCLUDE A STATE-OF-THE-ART 6-BIT ADC, A DEMULTIPLEXER, A POLY-PHASE FILTER BANK, A WINDOWING FUNCTION, A FAST-FOURIER-TRANSFORM CORE, A FREQUENCY-DOMAIN DATA ANALYSIS BLOCK, A DATA READOUT, A DIGITAL CONTROL UNIT AND TESTING FEATURES. TOLERANCE TO AT LEAST 500KRADS OF TOTAL IONIZING DOSE (TID) RADIATION WILL BE ACHIEVED BY IMPLEMENTING THE ASIC USING AN ULTRA-THIN GATE OXIDE CMOS TECHNOLOGY. LOW POWER CONSUMPTION WILL BE ACHIEVED BY EMPLOYING SPECIAL MULTIPLIER-LESS-ACCUMULATORS AND MULTIPLIER-LESS- BUTTERFLIES . THE POWER CONSUMPTION WILL BE FURTHER REDUCED BY MINIMIZING THE REDUNDANT STATES IN THE POLY-PHASE FILTER S FIR AND IFFT BLOCK. ADDITIONAL POWER-SAVING CAN BE ACHIEVED BY SWITCHING OFF THE ASIC S UNUSED BLOCKS, AND BY INTERNALLY DIVIDING THE CLOCK FREQUENCY. PHASE I WORK PROVIDED THE PROOF OF FEASIBILITY OF IMPLEMENTING THE PROPOSED SPECTROMETER ASIC. PHASE II WILL RESULT IN THE SILICON PROVEN ASIC S PROTOTYPES READY FOR COMMERCIALIZATION IN PHASE III.