THE PROPOSED PROJECT AIMS TO DEVELOP AN APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) FOR THE NASA S MICRO…
Award details are derived from public USAspending.gov records. Not a bid recommendation.
Award details
- Award ID
- 80NSSC18C0103
- Contractor
- PACIFIC MICROCHIP CORP.
- Awarding agency
- National Aeronautics and Space Administration
- Sub-agency / office
- National Aeronautics and Space Administration
- Award amount
- $755,000
- Period of performance
- May 24, 2018 – Apr 30, 2020
- NAICS
- 541715 — Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)
- PSC
- PSC AR11
Public award description
THE PROPOSED PROJECT AIMS TO DEVELOP AN APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) FOR THE NASA S MICROWAVE CORRELATION RADIOMETERS REQUIRED FOR SPACE AND AIRBORNE EARTH SENSING APPLICATIONS. THE RADIOMETER INSTRUMENTATION INSTALLED ON CUBESATS AND SMALLSATS IS REQUIRED TO HAVE SMALL VOLUME, LOW WEIGHT AND CONSUME LOW POWER. CURRENTLY USED CORRELATING RADIOMETERS RELY ON ANALOG SIGNAL PROCESSING, THUS ARE BULKY, POWER HUNGRY AND CANNOT BE REPROGRAMMED. ANALOG FILTER PARAMETERS TEND TO BE UNSTABLE OVER TEMPERATURE, POWER SUPPLY VOLTAGE, MAY DEGRADE OVER TIME, AND NEED TUNING. THE PROPOSED LOW-POWER, RAD-HARD ASIC WILL OPERATE WITH MICROWAVE CORRELATION RADIOMETER FRONT ENDS DOWN-CONVERTING THE RF TO UP TO 10GHZ IF QUADRATURE SIGNALS. THE ASIC WILL INCLUDE DIGITIZERS, BANDPASS FILTERS, CROSS-CORRELATORS, TOTALIZERS, SERIALIZERS, AN OUTPUT DATA INTERFACE, AND AN I2C INTERFACE FOR THE ASIC S PROGRAMMING. BANDPASS FILTERS WILL SPLIT UP THE DIGITIZED QUADRATURE IF INPUT SIGNALS INTO BANDS (UP TO 16), WILL CROSS-CORRELATE THE SIGNALS WITHIN EACH BAND, AND WILL SHIP OUT THE RESULTANT DATA IN A CONVENIENT FORMAT. INSTEAD OF ANALOG SIGNAL PROCESSING PERFORMING A STRICTLY DEFINED FUNCTION, THE ASIC WILL EMPLOY A DIGITAL SIGNAL PROCESSING WHICH CAN BE REPROGRAMMED TO ADOPT SPECIFIC PARAMETERS OF THE FILTER BLOCK SUCH AS THE NUMBER OF BANDS, EACH FILTER S CORNER FREQUENCY, BANDWIDTH AND FILTER S ORDER. A NUMBER OF INNOVATIONS WILL BE INTRODUCED TO THE ASIC IN ORDER TO COMBINE PROGRAMMABILITY, LOW POWER CONSUMPTION AND RADIATION TOLERANCE. THE PROJECT S PHASE I WILL PROVIDE THE PROOF OF FEASIBILITY OF IMPLEMENTING THE PROPOSED ASIC. PHASE II WILL INCLUDE FINISHING THE DESIGN, CHIP FABRICATION, TESTING AND DELIVERING THE ADC PROTOTYPES WHICH WILL BE READY FOR COMMERCIALIZATION IN PHASE III.
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