SAP PURCHASE REQUISITION: 4200242926--HIS SBIR PHASE III IS THE CONTINUATION OF THE PHASE I ENTITLED AVIONI…

Public award description

SAP PURCHASE REQUISITION: 4200242926--HIS SBIR PHASE III IS THE CONTINUATION OF THE PHASE I ENTITLED AVIONICS FOR SCALED REMOTELY OPERATED VEHICLES (ASROV) , PERFORMED BY COHERENT TECHNICAL SERVICES, INC. (CTSI) UNDER PURCHASE ORDER NNX08CC51P. DURING PHASE-I, CTSI DESIGNED A MICROPROCESSOR AND COMMUNICATIONS SYSTEM CAPABLE OF INTEGRATING A LARGE NUMBER OF INSTRUMENTATION SENSORS AND AIRCRAFT ACTUATORS INTO A REMOTELY MONITORED RADIO FREQUENCY DATA STREAM. THE SYSTEM CONSIDERED DETAILED REQUIREMENTS FROM EXISTING EXPERIMENTAL AIRCRAFT, AS WELL AS LOOKING AT CONCEPTUAL REQUIREMENTS FOR FUTURE SYSTEMS. LATENCY, RF BANDWIDTH, FAIL-SAFE MODES WERE ALL CONSIDERED IN DETAIL. THE SYSTEM DESIGN IS MODULAR AND FOLLOWS OPEN PROTOCOLS AND SOFTWARE STANDARDS WHERE POSSIBLE, WHICH PROVIDES FLEXIBILITY TO THE END-USER AND BROADENS THE RANGE OF POTENTIAL APPLICATIONS. SCOPE THE OBJECTIVE OF THIS SBIR PHASE III IS TO SUPPLY NASA LARC A PROTOTYPE SYSTEM WHICH IMPLEMENTS A SUBSET OF THE FULL ASROV DESIGN. THE PROTOTYPE ASROV UNIT WILL IMPLEMENT 3 SUB-SYSTEMS: THE SENSOR COMMUNICATION SYSTEM (SCS), THE BASIC FIGHT CONTROL SYSTEM (BAFCS) AND THE ACTUATOR CONTROL SYSTEM (ACS). EACH OF THE THREE SYSTEM COMPONENTS (SCS, BAFCS AND ACS) WILL PLUG INTO A CUSTOM MOTHERBOARD THAT WILL BE DESIGNED, FABRICATED AND POPULATED AS A PART OF THIS EFFORT. ALONG WITH THE DEVELOPMENT OF EACH OF THE SUB-SYSTEMS AND THE MOTHERBOARDS, THIS EFFORT WILL ALSO SELECT AND INTEGRATE A COMMERCIALLY AVAILABLE DATA-LINK. A MINI FORM FACTOR ETHERNET HUB WILL BE SELECTED OR DEVELOPED AND INTEGRATED INTO THE SYSTEM TO PROVIDE A SHARE BUS BETWEEN SCS, BAFCS AND ACS. TECHNICAL REQUIREMENTS TASK 1: DESIGN AND DEVELOP ACTUATOR CONTROL SYSTEM (ACS)  THE CONTRACTOR SHALL DESIGN A CUSTOM MOTHERBOARD CAPABLE OF HOSTING A XILINX SPARTAN 3 FIELD PROGRAMMABLE GATE ARRAY (FPGA) AND SUPPLY EXTERNAL PHYSICAL INTERFACE TO BOTH PULSE-WIDTH MODULATION (PWM) SIGNALS AND ETHERNET SIGNALS.  THE CONTRACTOR SHALL DEVELOP LOGIC CODE FOR THE FPGA THAT WILL HOST BOTH A MICROBLAZE SOFT-CORE PROCESSOR AND DIGITAL LOGIC CIRCUITRY CAPABLE OF GENERATING PWM SIGNALS.  THE CONTRACTOR SHALL IMPLEMENT SOFTWARE TO RUN WITHIN THE MICROBLAZE PROCESSOR THAT WILL READ ETHERNET MESSAGES AND CONVERT TO PWM SIGNALS DELIVERED TO THE PWM OUTPUT MULTIPLEXER.  THE CONTRACTOR SHALL IMPLEMENT A SIGNAL MULTIPLEXER AND SWITCHING LOGIC CAPABLE OF DRIVING A SET OF PWM OUTPUTS FROM EITHER ETHERNET MESSAGES OR A PASS-THROUGH OF PWM INPUTS. TASK 2: DEVELOP BASIC FLIGHT CONTROL SYSTEM (BAFCS)  THE CONTRACTOR SHALL DEVELOP SOFTWARE, CAPABLE OF BEING RUN ON A MICROBLAZE PROCESSOR, TO IMPLEMENT AT LEAST THREE CHANNELS OF SINGLE AXIS PROPORTIONAL DERIVATIVE FEEDBACK LAWS SUITABLE FOR VEHICLE FLIGHT CONTROL.  THE CONTRACTOR SHALL DEVELOP SOFTWARE CABLE OF BEING RUN ON A MICROBLAZE PROCESSOR TO PERFORM SINGLE-WAYPOINT GUIDANCE LOGIC. THIS GUIDANCE LOGIC SHALL DIRECT THE VEHICLE BACK TO A PREDEFINED LATITUDE, LONGITUDE AND ALTITUDE, AND ONCE THERE CONTINUE TO ORBIT THAT POINT WITH A CIRCULAR FLIGHT PATH. TASK 3: DEVELOP AND IMPLEMENT SENSOR COMMUNICATION SYSTEM (SCS)  THE CONTRACTOR SHALL DEVELOP A CUSTOM MOTHERBOARD CAPABLE OF HOSTING A XILINX SPARTAN 3 FPGA AND SUPPLY PHYSICAL INTERFACE FOR SERIAL STREAMS (RS-232 PROTOCOL), 32 ANALOG INPUT CHANNELS, AND ETHERNET  THE CONTRACTOR SHALL IMPLEMENT LOGIC CODE TO HOST A MICROBLAZE SOFTWARE CPU ON THE FPGA AS WELL AS INTERFACE LOGIC FOR SERIAL AND DIGITAL INPUT STREAMS.  THE CONTRACTOR SHALL IMPLEMENT SOFTWARE TO RUN WITHIN THE MICROBLAZE PROCESSOR THAT WILL READ INPUT SIGNALS AND FORM A USER DATAGRAM PROTOCOL(UDP) MESSAGE TO BE BROADCAST ON THE ETHERNET OUTPUT PORT. PERIOD OF PERFORMANCE THE PERIOD OF PERFORMANCE IS 4 MONTHS FROM THE EFFECTIVE DATE OF THE CONTRACT. DELIVERABLES THE DELIVERABLES FOR THE SBIR PHASE III EFFORT: TASK 1: ACTUATOR CONTROL SYSTEM (ACS