CURRENT AND FUTURE NASA MISSIONS ARE CONFRONTED WITH THE CHALLENGE THAT THE AMOUNT OF DATA COLLECTED BY ITS…

Public award description

CURRENT AND FUTURE NASA MISSIONS ARE CONFRONTED WITH THE CHALLENGE THAT THE AMOUNT OF DATA COLLECTED BY ITS SENSORS SIGNIFICANTLY OUTPACES THE DOWN-LINK BANDWIDTH. AS A CONSEQUENCE, INITIAL DATA REDUCTION HAS TO OCCUR ON-BOARD, USING ALGORITHMS SOPHISTICATED ENOUGH TO SUFFICIENTLY REDUCE THE AMOUNT OF DATA WHILE SIMULTANEOUSLY ENSURING THE PRESERVATION OF VALUABLE INFORMATION. THIS REQUIRES ENHANCED PROCESSING POWER ON-BOARD THE SPACECRAFT/DEVICE/TELESCOPE. WHILE FUTURE GENERATIONS OF RUGGED, RADIATION-HARDENED HARDWARE CAN BE EXPECTED TO DELIVER THE NECESSARY PERFORMANCE BY EMPLOYING HIGHLY HETEROGENEOUS ARCHITECTURES CONSISTING OF A COMBINATION OF FPGAS, DSPS AND MASSIVELY MULTICORE ARCHITECTURES, SOFTWARE DEVELOPMENT FOR SUCH DEVICES POSES A SIGNIFICANT CHALLENGE. WE PREPOSE TO DEVELOP TOOLS THAT FACILITATE AND ACCELERATE ALGORITHM DEVELOPMENT ON THESE HARDWARE DEVICES. THE TOOLS WILL ENABLE SCIENTISTS TO PROTOTYPE ALGORITHMS IN THE HIGH-LEVEL LANGUAGE THAT THEY ARE MOST FAMILIAR WITH WHILE SIMULTANEOUSLY BUILDING CODE FOR HIGH-PERFORMANCE COMPUTATIONAL HARDWARE.