THE PROPOSED 45 NM RADIATION HARDENED PLATFORM BASED STRUCTURED ASIC ARCHITECTURE OFFERS THE PERFORMANCE AN…

Public award description

THE PROPOSED 45 NM RADIATION HARDENED PLATFORM BASED STRUCTURED ASIC ARCHITECTURE OFFERS THE PERFORMANCE AND DENSITY EXPECTED OF A CUSTOM ASIC WITH THE LOW MANUFACTURING COST ASSOCIATED WITH A STRUCTURED ASIC. THE LOW COST, HIGH PERFORMANCE CUSTOMIZATION OF THE STRUCTURED ASIC PORTION OF THE CHIP IS MADE POSSIBLE BY THE 1-D 45 NM MASK-LITE PROCESS TECHNOLOGY. THE CHIP ARCHITECTURE IS OPTIMIZED FOR SENSOR DATA HANDLING APPLICATIONS IN SPACE AND THE DESIGN PROCESS PROVIDES FOR A SHORT DEVELOPMENT SCHEDULE. THE ARCHITECTURE PROVIDES A HARD MACRO MICROCONTROLLER CORE WITH VIA-ROM PROGRAM MEMORY, SRAM DATA MEMORY, CPU SUPPORT LOGIC, AN APPROPRIATE SET OF ANALOG FUNCTIONS, AND A STRUCTURED ASIC SECTION FOR APPLICATION SPECIFIC FUNCTIONALITY. A RAD-HARD BY DESIGN LOGIC CELL LIBRARY IS PROVIDED FOR THE STRUCTURED ASIC AREA OF THE DIE ALONG WITH A NUMBER OF PRE-COMPILED MACRO FUNCTIONS SUCH AS TIMERS AND SERIAL I/O TO REDUCE DEVELOPMENT TIME. THE 1-D MASK-LITE PROCESS PROVIDES A DRAMATIC REDUCTION IN THE MASK COST, ALLOWING LOWER VOLUME DESIGNS TO GAIN ACCESS TO 45 NM TECHNOLOGY, AND PROVIDES PERFORMANCE IMPROVEMENT OVER CONVENTIONAL VIA MASK STRUCTURED ASIC TECHNOLOGIES BY ELIMINATING METAL LAYER STUBS. STANDARD LOGIC DESIGN, VERIFICATION AND LAYOUT EDA TOOLS ARE USED TO COMPLETE A CHIP DESIGN. THE FIXED MICROCONTROLLER PLATFORM PORTION OF THE CHIP IS IMPLEMENTED WITH OPTIMIZED STANDARD CELLS RATHER THAN THE STRUCTURED ASIC LOGIC CELLS, RESULTING IN STANDARD ASIC PERFORMANCE LEVELS FOR THE CORE LOGIC.