FPGA LOW POWER DESIGN RULES
Award details are derived from public USAspending.gov records. Not a bid recommendation.
Award details
- Award ID
- W31P4Q10C0181
- Contractor
- Awarding agency
- Department of Defense
- Sub-agency / office
- Department of the Army
- Award amount
- $69,940
- Period of performance
- Jun 17, 2010 – Feb 15, 2011
- NAICS
- 541712 — Research and Development in the Physical, Engineering, and Life Sciences
- PSC
- PSC AD92
- Place of performance
- CA
Public award description
FPGA LOW POWER DESIGN RULES
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