SBIR/STTR Research Award

An AMBA-Compliant, Radiation Tolerant Tensor Core for Use in A.I. Applications

Award identifier 1e2939c8c90280463e2fd10a15a21638df1923f88f66b79bb30edddd7372df17Awarding agency National Aeronautics and Space Administration

Award amount

$124,931

Program and phase

SBIR · Phase I

Award year

2018

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
MICROELECTRONICS RESEARCH DEVELOPMENT CORPORATION
Proposal award date
2018-07-27
Contract end date
2019-02-15
UEI
M2WCCD39B593
Solicitation number
SBIR_18_P1
Topic code
Z8

Research abstract

A novel data processing accelerator intellectual property (IP) Radiation-Hardened-by-Design (RHBD) core for use in NASA future missions is proposed. The core is an artificial neural network accelerator based upon work done at Google, IBM, and others. The IP core is known as a tensor core and follows an architecture of matrix multipliers, accumulators, register files, and fast and abundant memory access. The tensor core will be developed to be Advanced Microcontroller Bus Architecture (AMBA) bus compliant and will feature an architectural approach to easily expand the data processing elements when more die area is available. The core will be developed on the trustedGlobal Foundries (GF)32nm Silicon on Insulator (SOI) process. There is extensive development currently occurring at this process technology, including NASA’s future High Performance Spaceflight Computing (HPSC) platform. The core is proposed as an effort to develop a data processing acceleration to decrease the down-link data bandwidth of future space missions. If more processing can be accomplished in situ, a given mission can be expected to require less data bandwidth, a problem that is becoming more critical with the ever increasing number of active missions. The IP core will be developed to be incorporated into other development at the 32nm process. The IP core will also be structured in such a way as to be incorporated into Micro-RDC’s future Reticle Programmable System on Chip (RPSoC) platform. The RPSoC is an active future platform, under development with funding from NASA and the Air Force, for digital and mixed signal designs to lower the cost of development at 32nm and to decrease lead-time from design inception to product delivery. The tensor core will be featured on this platform as a data acceleration core. The core will have RHBD techniques throughout the FEOL and BEOL to ensure that no data will be corrupted within the artificial neural network configuration or the data path.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

45 SBIR/STTR records share this UEI (2006–2019). Reported award amounts total $31,438,573. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

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