Tiled Silicon-Photomultiplier Array Read-Out Integrated Circuit

Silicon photomultipliers (SiPMs) are on the verge of revolutionizing all low light sensing and photon counting applications. The combination of low cost, compact size, and miniscule power consumption offers an attractive replacement for expensive, bulky, and power-hungry photomultiplier tubes (PMTs). SiPM laboratory setups typically include a bench full of heavy test equipment. The associated cost, size, weight, and power (c-SWaP) of this additional equipment present many practical challenges to the deployment of SiPMs, particularly in airborne and space missions.Many applications benefit from a large tiled array of SiPMs. However, a large SiPM array presents a challenge in proper signal conditioning and handling large volumes of data. The key to solving this challenge is a complete read-out integrated circuit (ROIC) that takes the quantized analog signal from the SiPM array and converts it into useful digital data for the user. This ROIC not only manages the SiPM array data but does so in a manner that significantly reduces the associated c-SWaP from a benchtop solution, a key requirement for practical SiPM deployment.The ultimate goal of this proposal is a fully integrated ROICthat interfaces to a SiPM array and is readily adaptable to both airborne and space deployed systems. The objective of Phase I is to develop the requisite components of a ROIC for photon counting and to assemble these components into a single channel of the ROIC. A test chip will be developed in Phase I to mitigate the risk of subsequent phases. This test chip will contain the relevant ROIC components, as well as a single channel of the ROIC, and will be designed, laid out, fabricated, and characterized in the Phase I effort.