SBIR/STTR Research Award

Photonic Memory Controller Module

Award identifier 07cafd7edf44486e724fe718b6e1fc7beca6a52ee0852c194c21d282f944ff1eAwarding agency Department of Energy

Award amount

$1,499,926

Program and phase

SBIR · Phase II

Award year

2018

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
FREEDOM PHOTONICS LLC
Proposal award date
2018-05-21
Contract end date
2020-05-20
UEI
FQ98KK1G9199
Solicitation number
DE-FOA-0001794
Topic code
04a

Research abstract

As computational density for high performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. General statement of how this problem is being addressed: A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high performance memory controller IP development to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM). What was done in Phase I: Columbia University coordinated the working group and subgroups to provide the system architecture and specifications for each small business consortium team members. Columbia developed high performance memory controller IPs and interfaces in FPGAs platform. Freedom Photonics developed the programmable, tunable laser using mature InP/GaAs processing. Analog Photonics developed the photonic transceiver and interconnect fabrics using silicon photonic processing. PLC Connections packaged the photonic transceiver and interconnect fabric chips and tunable laser chips and provide a low-loss and robust optical coupling mechanism. What is planned for the Phase II project: Columbia University will continue to coordinate the working group and subgroups to provide the system architecture and specifications for each small business consortium team members. Columbia will update high performance memory controller IPs and interfaces in FPGAs platform to meet Phase II goals and perform a final end of Phase II P-MCM demonstration. Freedom Photonics will develop and package a 17-channel integrated source laser array. Analog Photonics will design, fabricate and package switch, photonic transceiver, driver IC and interconnect fabrics using silicon photonic processing. PLC Connections will develop high density, low cost I/O packaging technology to interconnect the ICs and components developed in this program using dense fiber arrays to provide a low-loss and robust optical coupling mechanism, and deliver packaged prototypes to Columbia for system integration and demonstration. Commercial Applications and Other Benefits: The Photonic Memory Controller developed have wide commercial applications in data center and telecom markets.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

196 SBIR/STTR records share this UEI (2005–2023). Reported award amounts total $74,583,672. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy, Environmental Protection Agency, Department of Agriculture

Agency intelligence

Department of Energy

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