IP Access Gateway

This proposal aims to develop a back-end (BE) board, the “IP Access Gateway” (IPAG), in a commercial PCIe form factor, and build a COTS-based Continuous-Flow Trigger and Data Acquisition system (CF-TDAQ). The system monitors and synchronizes timestamps collected with local timing, and performs the event building of the data chunks from multiple detector sub-systems, front-end (FE) electronics and sensors. All FE signals are transported through optical fiber using our passive optical networks technology. Our miniature, radiation-hard on-detector FE interface modules provide the electro-optical conversion. The timing, event building,rigger/filtering, data reconstruction, and waveform analysis is performed on commercial GPU cards receiving data from IPAGs through PCIe. Both the direct optical transport capabilities, and the IPAG–GPU PCIe tandem, provide a massive increase in end-to-end data bandwidth, flexibility, and scalability, at a much lower cost. Furthermore, CF-TDAQ performs continuous acquisition, and multilevel triggering and filtering capability, all implemented in software. The foundation of CF-TDAQ is a ubiquitous, passive timing synchronization through our patent-pending General Timing Synchronization protocol (GTS). From a general information theory perspective, both the signals generated by particle detectors, and the network data flowing through the network links are transmission events. Our patent-pending Continuous Asynchronous TDC timestamps any transmission event with a local time reference provided by a free-running, low cost, highly stable oscillator array (OA). Numerical processing algorithms, running on GPU, provide timestamp matching, and determine the relative, end-to-end time relationships as a polynomial correction function, that is updated during every synchronization cycle. Local timestamps are converted to a single absolute time of the experiment with picosecond accuracy. Our approach eliminates the need for a custom, costly, and failure-prone Timing and Trigger Control system (TTC). The BE IPAG board interfaces between high-bandwidth digital data links from FE sensors, like silicon pixel trackers (e.g. CERN’s GBT) or FE ADCs, and the data network (NIC function) through embedded transceivers and high-density MTP or minipod multi-fiber connectors. Finally, the IPAG has a daughter card option which provides full waveform sampling analysis and allows for direct interfacing to analog signals generated by FE sensors. Our system has a theoretically unlimited scalability ranging up to billions of sensors and multi-Pbps aggregate input rates.