MWIR Staircase APD Receivers

AlInAsSb multistage APDs will be designed to achieve avalanche gain up to M = 1024, and excess noise of k < 0.02. The APD structure will be based on a staircase APD architecture, where composition and field are varied sequentially such that electron ionization is promoted and hole ionization is supressed. Using band-edge modeling tools and custom numeric simulation tools, in Phase I, the staircase APD designs will be optimized. Epitaxial wafers will then be grown that incorporate the design(s). Various area/perimeter ratio elements will be used to identify sources of dark current, and data from dark-current distributions of the various multi-staged APDs over a range of temperatures will be used to determine the locations and the dominant sources of dark-current contributors in the device. The gain, gain-bandwidth, linearity, and excess-noise performance of the APDs will be characterized as functions of the design of the gain stage and the number of gain stages used.Arrays will also be fabricated for integration into focal-plane arrays in Phase II.