SBIR Phase I: Highly Efficient Transmitter for Emerging Wireless Communication Systems in CMOS Technologies

The broader impact/commercial potential of this project will occur in the consumer electronics industry. Recent developments in mobile computing and wireless internet have led to an increasing demand for portable computers and smart phones equipped with wireless local area networks (WLAN) operating with multi-standard capabilities. The market for wireless communications systems exceeds 6 billion units per year, and full complementary metal-oxide-semiconductor (CMOS) transmitters promise a common technology platform to enable multi-standard, flexible, robust, integrated, and cheaper solutions. Improving the power efficiency and yield of high-performance power amplifiers (PAs) will have significant impact on the efficiency, reliability, and production cost of radio frequency (RF) transmitters, ensuring sustainable growth of the consumer electronics industry. The PA is responsible for approximately 22% of the overall power consumption of cellular base-stations while cooling represents 13%. For handheld devices, the PA is responsible for around 40% of battery power while transmitting information; hence, more efficient PAs will contribute to the development of greener technologies. Societal benefits will include power savings, more flexible and cheaper wireless communication devices. This Small Business Innovation Research Phase I project will focus on the design of highly-efficient linear RF transmitters suitable for broadband transceivers implemented in deep submicron CMOS technologies. Its specialized leverage is based on the digital control of PA sections such that the power consumption is fully correlated with the power delivered to the antenna, while the power gain and signal bandwidth are accurately controlled with a simple yet efficient digital algorithm. The research team proposes to develop a digitally-assisted linear PA architecture coupled to the antenna through a 1:3 turns ratio transformer and an optimized impedance matching network to achieve unique power savings of over 60% at moderate and deep back-off power levels. The current management based PA is strategically segmented and automatically optimized for best possible current efficiency. The architecture is flexible and well suited for the emerging IoT markets. For cases where the form factor is not an issue, the architecture can be equipped with a dynamic power supply system to further optimize for power. By incorporating these techniques, average power efficiency levels in the range of 25% at 9 dB back-off power are expected; these PAE levels surpass existing solutions by more than 60%.