Asymmetric Conductance Thermoelectric Cooling Modules for Cryogenic Applications

Thermoelectric coolers (TECs) have long been noted for their compact construction, high reliability, and clean, quiet operation, and they are now widely used in consumer products. However, TECs are inefficient devices requiring large electrical currents to provide a refrigerant effect. Even modest improvements in TEC performance would vastly increase the market potential of thermoelectric cooling, expanding its role into maintaining space science instrument components at cryogenic temperatures (<90K), as well as increasing adoption in consumer appliances such as refrigerators and air conditioners. microVection has identified a means of improving the efficiencies of TECs with minor design and fabrication changes. This involves shifting the peak temperature location through modification of the conductance in a simple and controlled manner. This was demonstrated first analytically and then by using a small cell of 3 couples (6 legs), and the results showed a significant (~30%) increase in the temperature differential of the cell at no heat load. The simplicity of the concept suggests that it offers a near-term, affordable cooling solution that can take advantage of both advanced materials and reductions in scale to improve temperature differentials by as much as 30%. Conversely, the same temperature differential can be achieved at lower input power levels, or at higher cold-side heat fluxes, with input power being reduced by as much as 60%. The overarching goal of the proposed effort is to bring high-performance thermoelectric cooling technology to a maturity suitable for the space science and commercial marketplaces, and to demonstrate analytically and experimentally that asymmetric conductance TEC designs offer significant advantages over conventional thermoelectric devices. The specific objective of the Phase I is to show that asymmetric conductance thermoelectric devices offer near-term improvements to thermoelectric coolers in high current design scenarios.