SBIR/STTR Research Award

High Performance Global Positioning System (GPS) M-Code Acquisition Engine

Award identifier f78cbebb2bc3cb7c988bbc6d854728a7fafde5a325dcd06383423798a26e27f7Awarding agency Department of Defense · Air Force

Award amount

$149,999

Program and phase

SBIR · Phase I

Award year

2016

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
RINCON RESEARCH CORPORATION
Proposal award date
2016-09-15
Contract end date
2017-03-21
UEI
FQT4ZAGJXKW3
Solicitation number
2016.1
Topic code
AF161-147

Research abstract

ABSTRACT: The Air Force seeks a trade study into a GPS M-Code Acquisition engine that utilizes the M-Prime version of the M-Code signal to provide the ability to operate more effectively in contested environments where high levels of jamming of the GPS system are to be expected. RRC will leverage the considerable advances in silicon technology and improved insights into computational algorithms that have occurred since the inception of the GPS modernization program to design a highly jam-resistant GPS M-Code acquisition solution with rapid TTFF. RRC plans for direct acquisition of the M-Code signal without reliance on C/A-code or other less resilient waveforms. The proposed approach uses a frequency-domain algorithm with a cross ambiguity function (CAF) processor to efficiently implement high processing gain with a large search space in delay (ITU) and Doppler (IFU). RRCs proposed architecture achieves a very high level of dynamic range and both coherent and non-coherent processing gain to meet the performance specifications.; BENEFIT: In this study, we identify a full GPS receiver implementation and SDR-based architecture that provides low cost and flexibility to support custom and unique GPS receiver applications with benefits to a variety of customers in the Federal marketplace. The study bolsters RRCs ongoing commitment and investment in GPS technology, including current efforts to develop a software-defined GPS receiver using an embedded ARM processor on a Xilinx Zynq System-on-Chip (SoC). A portion of our effort in Phase II and Phase III is the development of an acquisition engine architecture that readily integrates with an SoC type architecture for the software-defined receiver. An important output of the study determines whether the acquisition engine is a standalone ASIC that operates as a co-processor or as an accelerator as part of a multi-chip solution, or if the acquisition engine is integrated as part of the SoC itself. This study represents an opportunity for RRC to commercialize a complete GPS receiver solution based on the critical technological advances developed under this SBIR.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

15 SBIR/STTR records share this UEI (1992–2023). Reported award amounts total $5,149,543. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense

Agency intelligence

Department of Defense

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