Multi-Wafer-Stack Three-Dimensional (3D) Interconnect Manufacturing Technology

There is a longstanding need for a reliable, low-cost manufacturing method for assembling and electrically interconnecting high-density 2.5-dimensional and 3-dimensional multi-wafer stacks, including those composed of dissimilar materials and transistor technologies. However, many of the transistor technologies used in defense electronics are not compatible with the modern, full-wafer back-end-of-line processes used in commercial, largely foreign, semiconductor fabs. Thus, new approaches are required to create custom wafer stacks with a large number of interconnects in the vertical (via) and horizontal (trace) dimensions across an entire wafer and wafer stack.To address this need, inkjet-print (IJP) deposition and patterning of dielectric, electrical, and optical materials will be shown capable of interconnecting a multi-layer wafer stack, with high-density electrical and optical interconnection. In Phase I, the ability to print micron-scale electrical traces and 3D interconnections, and conformal adhesive layers will be demonstrated. Multi-wafer stacks will be fabricated, and electrically and mechanically tested.