SBIR Phase I: Ultra-High Speed In-Memory Searchable Dynamic Random Access Memory

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is provided by a novel data processing architecture, utilizing high-parallel in-memory computing for certain recurring and data intensive functions. Traditional computer architecture funnels all data through the CPU. Multiple CPU cores and very high clock frequencies are often used to address the issue of ever increasing demands on data processing capability. This is not sustainable from both an economical and an environmental standpoint, due to the power consumption involved and the lack of performance resulting from the limited parallelism of computation. Datacenters and cloud computing have long lost the ?green label? originally associated with internet technology and software. Their operators need to find more economical ways to process large amounts of data. Linear searches and data indexing can be performed economically within the memory itself, and at a several orders of magnitude increase in performance, due to the inherent parallelism of memory architecture. At the same time, this comes with significant power savings due to the elimination of data transport and CPU clock cycles involved. Datacenters will be able to serve more clients, with fever servers and less power consumption. This Small Business Innovation Research (SBIR) Phase I project investigates the feasibility of in-memory data search and compare algorithms which utilize the inherent repetitive structures of high density memory chips. Initial calculations suggest several orders of magnitude improvement in data throughput by in-place computation and simultaneous elimination of data transport. This addresses the industry's significant need for lower power solutions for so called "Big Data" applications, which are expected to continue their exponential rise through the Internet of Things (IoT), where cloud-stored sensor data are expected to eclipse data uploaded by humans in the near future. This Phase I project will perform a detailed architecture study along with a commercially viable and backward compatible communication protocol as well as behavioral models aimed at establishing the commercial viability and at attracting potential clients and licensing partners. Detailed simulations of the novel digital to analog sensing circuitry will thoroughly investigate the key intellectual property, laying the groundwork for the commercial realization of this innovation.