Field Programmable Gate Arrays FPGA Acceleration for Simulation & Test EnviRonment (FASTER)
Award amount
$1,473,692Program and phase
SBIR · Phase IIAward year
2016Award details
- Awarding agency
- Department of Defense
- Branch
- Missile Defense Agency
- Recipient company
- COLORADO ENGINEERING INC.
- Proposal award date
- 2016-06-16
- Contract end date
- 2018-06-17
- UEI
- D9RCJ7A3A8Y3
- Solicitation number
- 14.2
- Topic code
- MDA14-012
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- SWaPP-Efficient High-Precision Analog Ruggedized Conversion System
- High-Efficiency Long-Range Wireless Power Transfer
- High-Efficiency Wideband Linear Amplifier (HEWLA)
- High-Efficiency Wideband, Linear RF Amplifier for Naval Communications
- SPS-49 Agile PESA (SAP)
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Development of High Performance Computing (HPC) Technology for a Distributed Modeling and Simulation (M&S) Hardware Infrastructure (DASH)
- Development of High Performance Computing (HPC) Technology for a Distributed Modeling and Simulation (M&S) Hardware Infrastructure
- Parallel Adaptive Modeling and Simulation Through Intelligent Execution
- Development of High Performance Computing (HPC) Technology for a Distributed Modeling and Simulation (M&S) Hardware Infrastructure
- DASH: Dynamic, flexible computational acceleration using specialized hardware
Research funding history
66 SBIR/STTR records share this UEI (1993–2021). Reported award amounts total $27,212,008. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration, National Science Foundation, Department of Energy