SBIR/STTR Research Award

SBIR Phase II: Novel Capacitor-less Dynamic Random Access Memory Technology with Energy Efficiency, Manufacturability, and Scalability

Award identifier 188869d663374b7ab89278ef83b28a9a78a7eb9b2d9d4c94a877a41d2139df50Awarding agency National Science Foundation

Award amount

$744,115

Program and phase

SBIR · Phase II

Award year

2016

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
Alacrity Semiconductors Inc
Proposal award date
2016-03-01
Contract end date
2018-02-28
UEI
Not reported
Solicitation number
Not reported
Topic code
S

Research abstract

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to produce a new type of computer memory called Ferroelectric Dynamic Random Access Memory (FEDRAM). FEDRAM is cheap and can be mass-produced in current semiconductor manufacturing facilities. It also uses much less energy than current-state-of-the-art memories, and enables electronic devices to be much smaller in physical size. Commercially, FEDRAM works best as an embedded memory, which means they are ideally suited for products such as mobile phones where the processor and memory are on the same chip. Additionally, the same block of FEDRAM can be configured for high performance applications in addition to longer storage applications. This means that future devices will adapt to maximize power, performance, and usability. Due to the factors of price, performance, and low power, once FEDRAM is proven to work, it can potenitally be adopted in nearly every electronic device. This Small Business Innovation Research (SBIR) Phase II project addresses the commercialization questions of Ferroelectric Dynamic Random Access Memory (FEDRAM). In SBIR Phase I, it was shown that FEDRAM cells can be manufactured in an existing foundry with no new materials or equipment changes, and that FEDRAM has leading performance characteristics. The next step is to prove the same characteristics in an array, which would be considered a minimum viable product; this is the goal of SBIR Phase II. By proving this array, it will be possible to quickly scale the FEDRAM memory array into embedded applications for commercial deployment. The performance characteristics to be demonstrated are read/write latency, switching time, endurance, retention, and energy use.

Technology keywords

Not reported

Agency intelligence

National Science Foundation

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