Silicon Photonics Parallel Processor for High Performance Computing and Sensor Networks

High performance computing (HPC) and network systems have been experiencing dramatic growth in information processing capabilities. However, meeting the demand for increased capacity (larger bandwidths and higher data transmission rates) should be balanced by lower cost and energy consumption has become a limiting factor in the performance of such systems. Furthermore, HPC systems will be increasingly augmented by large numbers of sensors as part of the Internet of Things (IoT), which must be efficiently integrated. Intelligent Fiber Optic Systems Corporation (IFOS) has been working towards fiber optic sensor networks supporting thousands of sensors connected by multiple nodes of highly parallel processing interrogators, which enable simultaneous sampling of many sensors. Simultaneity provided by the parallel processing capability is a key enabler for applications such as monitoring ultrasonic wave propagation in large structures for efficient damage detection and structural health monitoring in large structures. Customized interleaved arrayed waveguide gratings (AWGs) with 100, 200 or 400 GHz channel spacing are core to ruggedized parallel processing systems. However, for large scale adoption, optoelectronic integration leading to reduced Size, Weight and Power, Performance, Cost (SWaP-PC) is critical. Silicon photonics manufacturing technology is promising in that (1) it can be an enabler for such integration, and (2) its high index contrast allows for shrinking of component size. Accordingly, IFOS proposes step-by-step development of silicon photonics chips that increasingly integrate parallel photonic processors with optical sources, routing modules, photo-detector arrays and eventually CMOS electronics. In addition to extending DOEs HPC capabilities the parallel processing photonic chip technology, which can provide a basis for distributed computing power and IoT sensory input, commercial applications will be widespread once mass production of photonic chips allows SWaP-PC reductions in comparison with present-day comparatively costly and bulky assembly of multiple optical components. In Phase I, IFOS will collaborate with Professor Watts’s group at MIT / AIM Photonics to develop a proof-of-concept integrated photonics design containing an 8-channel photonics processor (SOI – silicon on insulator) and compatible source, detector array and routing module for fabrication at MIT / AIM Photonics in Phase II. Algorithm concepts will be developed for dealing with any expected signal degradation due to silicon photonics imperfections. Commercial Applications and Other Benefits: On the consumer side, we envision iPhone size interrogation nodes. However, while the payoff can be considerable, the challenges are also significant. For example, silica-on-silicon technology allows for high quality AWGs supporting up to 128 channels, silicon photonics still struggles with the quality of 8 to 16-channel AWGs, not to mention integration of source, photo-detector and passive or active routing components