SBIR/STTR Research Award

SBIR Phase II: Low-density parity-check error correction for enhanced reliability of flash memories

Award identifier e7001ae702eaed8a5ebe807354a927a95f9a78fd30ccc63a94955c91f4a735b5Awarding agency National Science Foundation

Award amount

$750,000

Program and phase

SBIR · Phase II

Award year

2015

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
CODELUCIDA, INC.
Proposal award date
2015-08-12
Contract end date
2017-07-31
UEI
D22UFVK75TY3
Solicitation number
Not reported
Topic code
EI

Research abstract

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project are both technical and economic. The developed error-correction solutions will enable flash-memory-based devices to have higher capacities, higher reliability, and faster speeds at lower power while driving down the cost. This will have a major impact on mobile computing capabilities and enterprise storage by improving the efficiency and reliability of data centers, servers, and mission-critical storage that incorporate flash memories. Improved enterprise storage boosts the efficiency and growth of IT businesses, e-commerce, and financial trade. The solutions will also enable reduced power consumption and heat dissipation leading to greener systems. The benefits of the error-correction solutions are also applicable to the hard disk drive and communications industries. This Small Business Innovation Research (SBIR) Phase II project will develop and validate novel low-density parity-check (LDPC)-based error-correction for flash memory-based solid state drives (SSDs). SSDs are rapidly being deployed for both enterprise and consumer storage due to their fast speeds, low power, and low heat dissipation. But they bring numerous technical challenges stemming from the fact that reducing flash memory cell sizes leads to an unavoidable degradation in the reliability. With a trend of increasing die density to enable higher storage capacities, the industry is swiftly moving towards adopting LDPC codes to provide more powerful error-correction. However existing LDPC solutions use complex post-processing and multiple reads to bring down the error rates to the desired levels which lowers the read speeds, making them unattractive for future SSDs. Novel binary LDPC-based solutions will be developed for a range of parameters, and validated in hardware. The design method will be extended to develop new non-binary LDPC solutions which provide even greater reliability enhancements, leading to greater endurance in SSDs.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

2 SBIR/STTR records share this UEI (2014–2015). Reported award amounts total $899,961. Reported amounts are not federal obligations.

Phases: Phase II, Phase I

Agencies: National Science Foundation

Agency intelligence

National Science Foundation

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