SBIR Phase I: Area and Energy Efficient Error Floor Free Low-Density Parity-Check Codes Decoder Architecture for Flash Based Storage

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project will be a substantially more effective and efficient error correction scheme for flash memory than exists today. This will provide better reliability and extend the life of flash memory and will have a major impact on several technologies and markets such as enterprise storage at data centers, solid state drives, tablets, smart phones, and other consumer electronics. The flash memory market was estimated to include $30.1 billion in production and sales in 2013 and is expected to grow to $43.9 billion by 2018. The enterprise storage market is estimated to be $1 billion in 2014 and a robust growth is expected over the next few years. A substantial fraction of this market is related to error correction controllers for flash memories which are playing an even more important goal than ever considering the rapid scaling down and increasing capacities of flash memories which introduce more read errors than before. This Small Business Innovation Research (SBIR) Phase I project will address and develop tools to overcome problems that have traditionally prevented low-density parity-check (LDPC) codes from being deployed in flash memories and error correction controllers. A major problem is that these codes have error floors which prevent them from achieving very low error probabilities required in flash memories. In order to overcome this deficiency, new algorithms will be developed to understand the nature of the problem and to eliminate it using advanced signal processing methods. Area and energy efficient decoder technologies will be developed that make LDPC codes suitable for flash applications. This will include research optimizing LDPC based error correction systems for area and energy efficiency and elimination of the error floor problem. It will also include research on optimizing the detailed circuit design.