SBIR/STTR Research Award

Non Invasive Instrumentation For Single Event Effects (NIISEE)

Award identifier 1d782bc8a06577f656fb17ab439b8ba7d1b7486eb58dd659400737de365b630aAwarding agency National Aeronautics and Space Administration

Award amount

$124,874

Program and phase

SBIR · Phase I

Award year

2015

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
ADVENTIUM ENTERPRISES, LLC
Proposal award date
2015-06-17
Contract end date
2015-12-17
UEI
CJHNQPYZWBA3
Solicitation number
Not reported
Topic code
S3.09

Research abstract

On this Phase 1 project, Adventium will identify and address key hurdles to achieve Radiation Hardening by Software (RHS) for Single Event Effects (SEEs) for modern COTS processors. The primary benefit this approach will be to reduce the time and cost to deploy new space-based capabilities by leveraging power efficient, pervasive mobile computing processors. These processors, however, are not explicitly hardened against radiation (rad-hard) and, consequently, can accumulate uncorrected faults which violate time and space partitioning requirements and lead to mission failure. Current rad-hard space-based processors are custom components, predominantly used only by the aerospace community. They are costly and have limited capabilities and longer product refresh cycles compared to COTS processors. These factors contribute to a high barrier for entry for organizations who can contribute to and participate in Science Mission Directorate (SMD) missions, further impacting innovation. We will define requirements for, and establish the technical feasibility of Non Invasive Instrumentation For Single Event Effects (NIISEE), a cross-checking architecture that leverages built-in debug features in mobile COTS processors. NIISEE will detect transient and permanent SEEs in a space-based environment, while providing high availability and mission critical functionality. Our key innovation is to provide run-time, low-level, non-intrusive fault detection by repurposing a debug capability that already exists in fielded devices. This debug capability is far more capable than Joint Test Action Group (JTAG) scan chains, and is intrinsic in modern Advanced Reduced Instruction Set Architecture (RISC) Machine (ARM) embedded processors. While intended for debugging embedded applications and System On Modules (SOMs) during development, the logic blocks remain on-die in fielded devices.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

54 SBIR/STTR records share this UEI (2005–2023). Reported award amounts total $21,845,157. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Health and Human Services, National Science Foundation

Agency intelligence

National Aeronautics and Space Administration

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