SBIR/STTR Research Award

Ultra-Scalable Nonvolatile Graphene Memory

Award identifier 6b337d53fdd98a1a502f0c0db63c6ef4679751669c0f17ccdd9d42eda8c120e0Awarding agency Department of Defense · Air Force

Award amount

$749,747

Program and phase

SBIR · Phase II

Award year

2015

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
Harper Laboratories
Proposal award date
2015-02-10
Contract end date
2017-05-11
UEI
G691VJMAN2E4
Solicitation number
2013.1
Topic code
AF131-082

Research abstract

ABSTRACT:Nonvolatile memory (NVM) technologies are a critical component of modern satellites.These NVM chipsets perform tasks ranging from storing mission-critical boot code to large multi-gigabyte mission data recorders.This requirement for high-density NVM has shifted focus on to commercial CMOS FLASH.FLASH technologies are capable of high-density devices, compared to resistive or phase-change technologies, and typically scale on pace with Moores Law.However, charge pumps and other CMOS FEOL components face reliability concerns from TID and SEE (heavy ion) radiation exposure.As such, there is an inherent need for the introduction of intrinsically rad-hard carbon nanomaterials into commercial CMOS.Whereas previous wafer-scale processes for carbon nanomaterials have been hindered by device-to-device variation, CVD graphene sheets provide the opportunity to control material quality over a 200-400mm wafer.Harper Laboratories, LLC, the Georgia Institute of Technology, Novati Technologies, and BAE Systems will manufacture a graphene-based FLASH bit cell that is CMOS-compatible and capable of forming multiple commercial suppliers.Novati technologies will provide FEOL and BEOL CMOS fabrication capabilities that, combined with Harper IP, will ready a graphene-based FLASH technology for transition to a high-volume CMOS foundry in Phase III.BAE Systems will provide rad-hard testing to validate the technology.BENEFIT:The general anticipated benefit would be a graphene-based FLASH memory technology capable of supporting high-density space memory applications.A secondary benefit is the development of a CMOS-compatible process for patterning graphene devices with low device-to-device variation across a 200-400mm wafer for which a varying number of commercial applications could arise (graphene on-chip interconnects and transistors).In particular, the introduction of a CMOS-compatible graphene processes can provide disruptive shifts in the global semiconductor industry, including post-CMOS technologies.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

4 SBIR/STTR records share this UEI (2013–2015). Reported award amounts total $1,149,081. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Science Foundation

Agency intelligence

Department of Defense

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