SBIR Phase II: Defect Mapping Instrument for Optimizing Wafer Manufacturing Process

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is that it will benefit the semiconductor manufacturing industry by providing a metrology tool that increases yield and reduces manufacturing cost. This project develops a non-contact, non-destructive tool that enables rapid wafer scan, producing a subsurface defect map to locate and minimize defects during integrated circuit manufacturing. The end user will benefit from the lower cost of electronics resulting from increased yield. Environmental benefits include reduction of wasted wafers and associated materials and chemicals used during wafer processing. Other use of this technology is as a laboratory instrument, providing a new subsurface characterization tool to the scientific community. Semiconductors are ubiquitous in our lives and the trend towards making them (and the products which house them) faster, cheaper and smaller are clear. The industry is vocal in its need for testing equipment to keep up with this trend, but current technologies fall short. This Small Business Innovation Research (SBIR) Phase II project is to develop an inspection tool that is capable of detecting subsurface features and defects for semiconductors wafer inspection. In the wafers manufacturing, starting from the bare wafer, each step can lead to defects, which, if not detected, can lower yield and increase cost. Certain buried defects are not detectable using standard imaging techniques due to the presence of absorptive layers. This SBIR Phase II project describes a non-contact, non-destructive tool that utilizes an optical/acoustic technique that enables rapid wafer scan, producing a subsurface defect map to locate and minimize defects during integrated circuit manufacturing. Successful completion of the Phase II will lead to prototype work and commercialization.