SBIR/STTR Research Award

SBIR Phase I: Dynamic Mode Adjustment Between High Performance and Power Saving States

Award identifier ab5ae2821a51329a2faaf93ef190bd7ca6fd0e90d628667de2e3647f4faf646bAwarding agency National Science Foundation

Award amount

$150,000

Program and phase

SBIR · Phase I

Award year

2014

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
PACKET DIGITAL LLC
Proposal award date
2014-01-01
Contract end date
2014-12-31
UEI
MPCASPRLSZA7
Solicitation number
Not reported
Topic code
EI

Research abstract

This Small Business Innovation Research (SBIR) Phase I project will research, design and demonstrate a new technique for dynamically controlling the operating mode for DRAM devices. Today memory is set to the highest performance and highest power mode at boot regardless of usage, an antiquated approach creating thermal hotspots and wasting power. The intellectual merit is a combination of both frequency and voltage scaling by monitoring activity to boost memory bandwidth under high demand conditions and resume lower frequency modes when higher performance is unnecessary. Traditionally, operating mode of memory is fixed at levels that will provide the peak performance required and is not modified while the system is running. The research objectives are to select a target architecture and platform, conceptualize dynamic mode switching by creating simulation models of the memory and determine minimum required supply voltages and frequencies, build an evaluation unit, and test and demonstrate activity-based dynamic mode switching. This dynamic mode concept will allow the memory to speed-up to complete activities sooner and optimize power consumption in real time providing both system and performance benefits for consumers and resulting in the world?s first dynamic real-time architecture for varying memory clock frequency and voltage based on activity. The broader impact/commercial potential of this project is significant power savings to address green energy initiatives and poor battery life across consumer, business, and military electronic market segments. This includes memory applications such as data center servers, notebooks, and extending battery life in handheld electronics. This technology will enable smaller, more flexible, and more easily integrated power management with an improved cost/benefit ratio. Commercially, annual memory module shipments are expected to reach over 1 billion units by 2014. With market penetration rate of 0.2% there is a commercial potential of $5 million in revenue in 2017 and $11 million by 2019. With this technology in their mobile devices the consumer will see reduced power consumption resulting in extended battery life, lower heat dissipation and cooling costs and increased reliability. Compared to statically assigning a power saving mode the consumer will see faster response to application starts and improved performance, throughput, and bandwidth while still saving power and costs during less demanding activities. This project is a truly unique project that has far reaching benefits for today?s handsets, tablets, PCs, and servers.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

7 SBIR/STTR records share this UEI (2008–2016). Reported award amounts total $3,359,311. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Health and Human Services, Department of Defense, National Science Foundation, Department of Energy

Agency intelligence

National Science Foundation

Back to SBIR/STTR Research Awards

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