SBIR/STTR Research Award

Advanced 150V GaN Solid State Power Amplifier Topologies for High Power Microwave Applications

Award identifier ffaa217ecb154675077df21abcde72a56ce042eb60524de512061dd13ca00234Awarding agency Department of Defense · Navy

Award amount

$997,886

Program and phase

SBIR · Phase II

Award year

2025

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Award details

Awarding agency
Department of Defense
Branch
Navy
Recipient company
INTEGRA TECHNOLOGIES, INC.
Proposal award date
2025-09-02
Contract end date
2026-10-30
UEI
UL1XJ5MK7QB5
Solicitation number
23.1
Topic code
N231-062

Research abstract

Base Integra will focus on developing a SSPA (Topology #4, Integrated Feedback Amplifier), This SSPA will breakthrough limitations to enable operation at 50% duty cycle while simultaneously reducing the Cgs and Cds for increased instantaneous bandwidth. Integra will focus on 3 specific areas: 1)design & fabricate a new 150V GaN/SiC chip including Integra patent pending advanced transistor structure which reduces intrinsic resistance 10X compared to existing GaN/SiC transistors. 2)Integrate several of the newly fabricated 150V GaN/SiC chips into a single packaged multi-kW transistor. 3)Design & fabricate the Integrated Feedback Amplifier in a pallet form using the fabricated 150V GaN/SiC packaged transistors. The SSPA topology is based on Integra’s 150V GaN/SiC transistor chip with 0.25mm gate length designed and fabricated on its proprietary AlGaN/GaN/SiC HEMT epitaxial wafer structure. Integra will include chip design variants on the mask as a risk mitigation. Integra will also build transistors in our standard CuMo based packages as well as the new higher thermal conductivity diamond composite package. The diamond package enables the SSPA to operate at longer pulse widths & higher duty cycles.     Option For the Phase 2 Option, 2 wafers lots are also proposed to investigate the potential for further performance improvements with an epitaxial structure based on InAlN/GaN/SiC HEMT designed to allow 150V operation with 0.25mm gate length. Given the anticipated ~2x higher current density that this material offers compared with the established AlGaN/GaN structure, a new mask set will be required since the total gate periphery of these chips will be roughly 50% the size of the baseline design, which translates into 50% reduction in input and output gate capacitance Cgs and Cds, thus facilitating even wider bandwidth for future HPM requirements. The wider bandwidth with lower parasitic losses discussed in the Phase 1 Final Report and therefore with improved efficiency and thermal behavior.  InAlN/GaN is routinely researched for high frequency applications at Ka-band due to the increased current and power density compared to AlGaN/GaN which results in a given   a smaller gate periphery and less parasitic elements for a given power level. Integra strongly believes the benefit of this option is very high with low risk with potential to be a disruptive technology for US DoD.  For both the Base and Option, the 150V GaN/SiC Integrated Feedback Amplifier will be validated on a pallet, a commonly used in the industry which Integra manufactures. The performance results from Phase 1 and the technical planning effort for Phase 2 have indicated that the goal of realizing the 5kW Integrated Feedback Amplifier with 1GHz bandwidth at 1.5-2.5GHz for HPM applications is achievable. Integra would plan to deliver a demonstration pallet to ONR for testing if desired.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

6 SBIR/STTR records share this UEI (2013–2025). Reported award amounts total $2,503,848. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Aeronautics and Space Administration, Department of Defense, Department of Energy

Agency intelligence

Department of Defense

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