SBIR/STTR Research Award

Low Cost Universal Reliability System On-A-Chip for Multi-Channel Characterization

Award identifier 085bdd1e6eb10fcac756bdfa141bb2674c20a670b2e672a83bc431ddbe7b591aAwarding agency Department of Defense · Air Force

Award amount

$749,960

Program and phase

SBIR · Phase II

Award year

2013

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
ULTRA COMMUNICATIONS, INC.
Proposal award date
2013-05-03
Contract end date
2015-08-02
UEI
XJWHA6PGHM25
Solicitation number
2012.1
Topic code
AF121-166

Research abstract

ABSTRACT: Close-in sensors can be used to embed reliability and functional RF test capability directly on to RF chips in order to reduce the cost and complexity associated with carrying out reliability studies and product characterization. Recent advancements in silicon technology have enabled the development of close-in sensors and stimulus components ranging from direct current (DC) to RF signals. One can envision a universal reliability system on-a-chip (RFRELIC) for RF characterization where DC and AC sensors/stimulus may be implemented monolithically to realize a low cost system. This proposal proposes a suite of test structures, stimuli and sensors to embed test capability directly into integrated circuits. BENEFIT: This technology has potential to revolutionize assessing complex electronics for military use. Integration of voltage regulation to supply the necessary voltages and waveforms to multiple channels; on-chip RF sources for input stimuli; and digital controllers and monitors to coordinate testing activities such as supplying power to the Device Under Test (DUT) and capturing device performance simultaneously as the stressors are being applied is possible. Beyond HTOL and acceptance testing on-chip, on-chip Built-In-Test (BIT) has other applications to increase system reliability. An integrated circuit can monitor and report state of health. In the event that a circuit within a chip has failed, the chip would re-route to an alternate parallel path and greatly extending the reliability of the chip. For example if an amplifier failed, you could switch to a parallel amplifier. If a duplicate circuit does not exist, the signal could still be re-routed to an alternate path which might yield result in a soft failure versus non-operating condition. The additional cost/size of Built-In-Test (BIT) and parallel paths in RF integrated circuit processes will be minimal given today"s scale of integration.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

58 SBIR/STTR records share this UEI (2005–2017). Reported award amounts total $22,990,939. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy

Agency intelligence

Department of Defense

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