Automated Cache Performance Analysis and Optimization in Open|SpeedShop

While there is no lack of performance counter tools for coarse-grained measurement of cache activity, there is a critical lack of tools for relating data layout to cache behavior to application performance. Generally, any nontrivial optimizations are either not done at all, or are done by hand requiring significant time and expertise. To the best of our knowledge no tool available to users measures the latency of memory reference instructions for particular addresses and makes this information available to users in an easy-to-use and intuitive way. Such a tool would be beneficial to both the DOE and the general public, as it would reduce the needed optimization time and decrease time to solution. In Phase I, we will enable Open|SpeedShop to gather memory reference latency information for specific in- structions and memory addresses, and to gather and display this information in an easy-to- use and intuitive way to aid performance analysts in identifying problematic data structures in their codes. Commercial Applications and Other Benefits: This tool will be primarily designed for use in the supercomputer domain as well as grid, cluster, cloud-based parallel e-commerce, and engineering systems and middleware. The result of this work will be a tool of broad international use across several scientific, commercial, and cloud computing communities.