SBIR/STTR Research Award

SBIR Phase I: EI/ES6: Low Power Consumption Digital IC Systems

Award identifier fc0b522d2887325672902024a8671bfd383d1dacf98edd4dd530e58d0bf314bcAwarding agency National Science Foundation

Award amount

$150,000

Program and phase

SBIR · Phase I

Award year

2013

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
Granite Mountain Technologies, Inc
Proposal award date
2013-01-01
Contract end date
2013-06-30
UEI
RNSDS6NPKXV4
Solicitation number
Not reported
Topic code
EI

Research abstract

This Small Business Innovation Program (SBIR) Phase I project commercializes a technology that reduces the energy consumption in digital electronics on average by a factor of three. The solution applies across the complete semiconductor marketplace. The power advantages are derived based on designing multi-synchronous digital electronics. A next generation design flow is developed for multi-synchronous systems based on a novel method called relative timing. Relative timing enables the application of the standard single clock frequency Electronic Design Automation (EDA) tools and flows to be seamlessly applied to the design of multiple timing domains in a single digital integrated circuit. No modifications to the standard cell libraries are required. Some additional EDA is necessary to support the extended concurrency and synchronization provided by additional multi-synchronous circuit Intellectual Property (IP) primitives. These IP blocks enable lower power, reduced area, and higher performance than single frequency designs. Timing constraints in these multi-synchronous systems are based on formal verification and therefore are proven correct and complete. System design productivity is enhanced due to design modularity. This project validates the method by developing a product-ready semiconductor design that demonstrates a significant competitive advantage in power, area, and performance against a traditional single frequency design. The broader impact/commercial potential of this project addresses the need for reduced energy consumption in digital electronics and is rooted in the exponential growth in transistors on integrated circuits. Previously, as designs became power limited, new transistor technologies were introduced. Each logic family provided lower power and better performance. No new transistor technology is on the horizon, making design contributions to energy efficiency critical. The localized efficiency of multi-synchronous design is one of very few design methods that provide significant energy reduction. Successful commercialization will result in this technology being applied across the semiconductor industry to products ranging from performance cloud compute servers to medical electronics and sensors. Industry wide growth will occur through EDA and custom circuit IP products that enable the development of multi-synchronous architectures. Open market and strategic partnerships with world class semiconductor companies for training, consulting, and early product development will reduce early risk and develop market acceptance. Ultra-low power medical applications such as digital hearing aid devices particularly benefit from multi-synchronous technology. Increased battery life reduces product cost and improves the quality of life for seniors and the disabled. Similarly, ultra-low power biomedical wireless sensors likewise provide societal benefit.

Technology keywords

Not reported

Agency intelligence

National Science Foundation

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