SBIR/STTR Research Award

Radiation-Hardened Low-Power ADC for Particle Detectors

Award identifier df27ee081baa82dde6c9a12c032395e8859c0f967b254be6ea4818d1ef2db54eAwarding agency Department of Energy

Award amount

$1,006,630

Program and phase

SBIR · Phase II

Award year

2012

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
RIDGETOP GROUP INC
Proposal award date
2012-08-08
Contract end date
2014-08-07
UEI
CRLUWHJZHLU8
Solicitation number
DE-FOA-0000676
Topic code
61 a

Research abstract

Particle detectors for nuclear physics and high energy physics experiments require high performance, high sensitivity digitizers for read-out electronics. Analog-to-digital converters (ADCs) are used in such applications but limit experimental results because of a restrictive combination of speed, resolution, power, and radiation-hardness. Many instruments need very high channel counts, a costly requirement and a very difficult objective to achieve where densely packed electronics generate too much heat. General statement of how this problem or situation is being addressed. This Phase II will result in the design and fabrication of an innovative high-performance, ultra-low-power device that will incorporate 16 ADC channels on a single chip. Using radiation-hardened-by-design (RHBD) techniques and the novel topology developed and verified in Phase I, the ADC chip will be able to provide the linearity and resolution required for use in a wide range of experimental instrumentation at HEP facilities like RHIC and LHC, and in nuclear physics labs at Jefferson Lab, Oak Ridge, and others, while also lowering costs because of the high degree of channel density. What was done in Phase I? Phase I saw the design, development, and simulation of a behavioral model of the complete ADC, along with transistor-level designs of key subcircuits, including operational transconductance amplifiers (OTA), a high-speed comparator, a radiation-tolerant bandgap voltage reference (BGR), a bootstrapped high-linearity sampling switch, and a complete 2.5- bit pipeline stage. This work validated the feasibility of the overall ADC design approach. What is planned for the Phase II project? The Phase II ADC design will lead to a design and fabrication of a chip encompassing an array of 16 ADC channels, each meeting key functionality goals, including 40 MS/s sampling rate, 12-bits resolution at 10.5 11.0 effective number of bits (ENOB), and a very low power dissipation of 12 mW / channel. It will also exceed the required level of TID hardness of 3.5Mrad (Si) as well as achieve extreme tolerance to other radiation effects (e.g., neutron fluencies, SEUs, SEFIs). Commercial Applications and Other Benefits: High performance ADCs hardened to extreme levels of radiation are key components of the LHC experiment, the largest scientific experiment ever constructed. Hundreds of thousands of qualified ADCs will be needed for one detector instrument alone. The currently used ADCs at LHC will be changed to more radiation tolerant and less power consuming ADCs during the upgrade process to High Luminosity Hadron Collider (HL-LHC). Tens of thousands of new radiation hardened, low-power ADCs have been planned to be used in the upgraded Relativistic Heavy Ion Collider (RHIC) as well. Another scientific application for this ADC is NASAs flagship mission to the Jovian moon Europa, as the radiation levels require this type of device. The ADC can be used in defense applications, such as missile control, and federal and commercial space applications. Medical imaging is another application for the ADC

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Agency intelligence

Department of Energy

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