Massive Parallel SAR Scene Simulator

ABSTRACT: The Air Force has a requirement to test Synthetic Aperture Radar (SAR) systems in an RF Hardware-in-the-Loop (HITL) simulation. The simulation requires that a large number of computations to determine the simulated target and clutter signals be performed in a short amount of time to adhere to the timeline requirements. The current method of generating the target and clutter signals employs a mix of analog and digital processing. The recent technological advancements of high-speed, high-density Field Programmable Gate Arrays (FPGA) now allow for an all digital solution. Technology Service Corporation (TSC) proposes to develop a SAR Scene Simulator (SARSSim) system using an FPGA-based architecture to meet all of the Air Force"s requirements. TSC will first define the SARSSim system requirements. The computations required to generate the desired signals will then be defined. Next, TSC will develop a top-level architecture to meet the system requirements. Critical portions of the architecture will be evaluated using an FPGA-based demonstration board. The results generated in Phase I will be used to generate a development plan for a Phase II Proof-of-Concept SARSSim system. BENEFIT: A demonstrated SAR Scene Simulator (SARSSim) system Proof-of-Concept system should be of great interest to RF Hardware-in-the-Loop (HITL) simulation facilities in the Air Force, Army, and Navy. Such a system could be utilized by the HITL facilities to perform the many real-time computations that are required. Commercial SAR companies will also benefit, since this technology could be used onboard aircraft to generate real-time SAR imagery allowing immediate imagery analysis to be performed.