SBIR/STTR Research Award

SBIR Phase I: On Demand Verification for Analog Integrated Circuits

Award identifier fe2f0901c59eb7856d8fd05ee744b86288f6ad9aedf61a8f8bc96f84b5a45017Awarding agency National Science Foundation

Award amount

$150,000

Program and phase

SBIR · Phase I

Award year

2012

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
Zipalog, Inc.
Proposal award date
2012-07-01
Contract end date
2012-12-31
UEI
GHFREGV4PQU7
Solicitation number
Not reported
Topic code
EI

Research abstract

This Small Business Innovation Research Phase I project proposes an on-demand verification (ODV) facility for analog / mixed-signal application (A/MS) specific integrated circuits (ASICs). The technology innovation is a virtualized cloud-based verification platform that supports all aspects of A/MS ASIC verification for integrated circuit design centers, including behavioral modeling, test bench management, simulation planning, simulation farming, and data mining. The proposed ODV system scales with ASIC complexity and design staff expansion by leveraging cloud computing resources. More importantly, the proposed verification resources can be scaled down once verification tasks are complete, creating opportunities for small design centers to create high quality designs with competitive cost structure for design operations. The initial proof-of-concept design system will be equipped with open source EDA design, modeling, and verification software tools. The modularity inherent in the proposed verification platform will also support the installation of best-in-class commercial partner software solutions and their use in ASIC verification activities by subscribers to the ODV facility. The broader impact/commercial potential of this project is to improve the competitiveness of U.S. semiconductor industry by reducing A/MS design verification cycle time, improving first pass design success and reducing time-to-market. The complexity of A/MS ASIC design has aggressively followed Moore?s law, but innovations in design verification have not. Small, fabless analog design centers in particular struggle to compete in complex design creation given the existing EDA licensing model. Equipping a small design team with the proper verification and analysis tools, for example, is financially equivalent to quadrupling the staff. The results of this research work will lower barriers to entry and innovation for small and emerging companies by providing a scalable verification service without the onerous burden of additional software licensing costs and infrastructure overhead. In addition, the ODV system enables more collaborative innovation among the market players through a cloud-based platform. This would materially benefit the existing semiconductor market participants and open the door for new participants.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

3 SBIR/STTR records share this UEI (2012–2014). Reported award amounts total $1,050,000. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Science Foundation

Agency intelligence

National Science Foundation

Back to SBIR/STTR Research Awards

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