Dual Speed Read Out Integrated Circuit (ROIC)

This SBIR requires the development of an innovative dual speed ROIC (DSROIC) architecture, mated to a detector array within the band of interest and with suitable response speed. According to the solicitation, this effort will establish a DSROIC concept capable of performing conventional staring imaging at video frame rates, while simultaneously being able to process and detect each frame at a higher rate. The solicitation further states that the ability to smartly integrate higher frame rates will provide an overall enhanced image quality and provide an automatic integration time providing the user enhanced image quality. In addition to the greatly increased frame rate, desired features include specialized functionality that will allow for windowing/binning, zoom, autonomous signal processing, programmable frame time, programmable conversion gain, and analog to digital conversion per pixel. RNET is proposing to develop a real-time, digital DSROIC architecture with enhanced performance that will provide the much needed improvements in future FPAs. The envisioned DSROIC architecture focuses on the combination of the front-end of split channel pixel cell design, embedded analog-to-digital conversion (ADC), and programmable features.