Graphene synthesis on large-area silicon wafers suitable for manufacture

The objective of the Phase I project was to demonstrate graphene synthesis on a silicon (Si) wafer with (001) orientation without relying on the transfer of a template layer or any other material from one substrate to another. This Phase I objective was successfully demonstrated using symmetry transformation layers (STL). The proposed Phase II objective is to further develop the STL concept for graphene synthesis. Reduction in maximum processing temperature will be pursued in Phase II. Maximum temperature of 1150 C or less is possible. Refinement of graphene synthesis parameters will be undertaken to improve the structural and electrical characteristics of graphene produced by this method. Characterization of the transport and optical characteristics of graphene will be performed with potential applications (e.g. rf communications, sensors, digital imaging and displays) in mind. Devices from one or more of these application areas will be demonstrated to assess potential product feasibility. Marketing of graphene/Si integrated materials is planned.