SBIR Phase II: Massively Dense 3D Integrated Memory

This Small Business Innovation Research (SBIR) Phase II project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional (3D) integrated memory (3DIM) architecture achieved using a single substrate without need to assemble multiple die or wafers together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, the memory elements will scale to smaller dimensions without reducing the current through the device, thereby resulting in a dense memory array architecture with improved signal-to-noise ratio for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with an isolation diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications. The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, mobile internet and other portable devices using nonvolatile memory. Memristive device arrays impact numerous commercial markets including flash and embedded memory, and offer orders of magnitude more density as compared to conventional memory. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate multiple substrates and bond them together, thereby simplifying the fabrication process, reducing manufacturing cost and increasing yield. In addition to portable devices, the proposed device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and heavy ion radiation. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and faster than competing technologies. Memory arrays will be fabricated in a commercial foundry and scaled to smaller dimensions throughout the Phase II project.