SBIR/STTR Research Award

Low Cost, Reconfigurable, Multi-Channel Pulse Processing Platform

Award identifier 2bc74356ac4f622d1505561016792d941622ff31dac66efcb4f85a0d0a67ed04Awarding agency Department of Energy

Award amount

$1,000,000

Program and phase

SBIR · Phase II

Award year

2011

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
VOXTEL, INC.
Proposal award date
2011-08-15
Contract end date
2013-08-14
UEI
N2KECNUUMBF4
Solicitation number
DE-FOA-0000508
Topic code
59 b

Research abstract

Planned science instruments require timeofflight (TOF) detectors with subpicosecond resolution, high count rates, and a large number (hundreds of thousands) of parallel channels. Timetodigital converters (TDCs) are effective for TOF measurement. With few exceptions, subnanosecond TDCs have been implemented as applicationspecific integrated circuits (ASICs), which are expensive and timeconsuming to develop. It is also not yet possible to implement analog signal measurement and processing close to a largeformat detector array. A TDC with improved timing resolution and channel count is being implemented in an inexpensive, reconfigurable FPGAbased form to minimize cost and address diverse applications. Signal TDC measurement and pulse processing functions include binary pulse processing (BPP), single and multiple timeoverthreshold (TOT/MTOT) measurement, coincidence detection, and auto/cross correlation. 1024 channels with 850 ps TOF resolution can be integrated into a ca. 4 & quot; 5 & quot; printed circuit board, and as many as 512 channels can be implemented with one or more of these functions: sub20ps resolution TDC, 100MHzscale perchannel count rates, and realtime histogramming and coincidence detection. All Phase I program objectives were met and many were exceeded. The 64channel prototype board achieved 25ps TOF resolution, and TOT, MTOT, and auto/cross correlation were demonstrated on a subset of the channels, using programmable amplification, pulse shaping, and threshold interface boards. The TDC/BPP board was calibrated and tested using InGaAs detector arrays, Geigermode InGaAs APDs, and silicon photomultiplier (SiPM) detectors, using a gigabit Ethernet connection, with favorable results relative to more expensive, commercially available 1channel instruments. The Phase I prototype will be ported to a nextgeneration FPGA with onethird the cost, onequarter the power, four times more channels per board, and TOF resolution two times finer. An instrument will be demonstrated with a 1024channel lowcountrate (subnanosecond) mode, and a highpulsecount mode with as many as 512 TDC channels, including TOT, MTOT, and auto/crosscorrelation. Commercial Applications and Other Benefits: When completed, the technology will be made available to developers of instruments for HEP and nuclear physics. NonDOE applications include radiation detectors for nuclear instruments, biomedical imaging devices such as positron emission tomography (PET) imaging systems and Xray imaging devices, and military applications such as laser radar (LADAR).

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

235 SBIR/STTR records share this UEI (2000–2021). Reported award amounts total $86,180,717. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, Department of Energy, National Aeronautics and Space Administration, Department of Commerce, Department of Homeland Security, Environmental Protection Agency

Agency intelligence

Department of Energy

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