Highly Scalable Metal Source/Drain"Schottky"CMOS for Mitigation of Parasitic Bipolar Effects and Improved Power, Speed and Radiation Performance

ABSTRACT: Avolare 2, LLC proposes the simulation and quantization of single event effects (SEUs) on highly scaled (i.e., sub-65 nm gate length) metal source/drain"Schottky"CMOS (SB-CMOS) transistors. Mixed-mode 2D device/circuit simulations of an SRAM core (back-to-back inverters) subjected to an energetic particle strike will be modeled. Avolare 2"s proprietary Monte Carlo TCAD tool"WhiteCap"will be used to model the inverter not affected by the strike (a SPICE-like circuit simulation using compact models) and will also perform full 2D device-level simulations of the inverter subjected to ionizing radiation. N and p type devices, metal and conventional doped source/drain structures, gate lengths from 65nm to 10nm and uniformly doped well and double well (buried p-n junction) architectures will be investigated. The threshold LET the minimum LET that causes upset will be determined for each combination of parameters. Comparison/plots of threshold LET for metal and conventional doped source/drain structures with device type, gate length and well structure as parameters. Determination of threshold LET advantage of metal source/drain vs doped source/drain structure BENEFIT: The successful development of rad-hard metal source/drain"Schottky"CMOS (SB-CMOS) technology and the quantization of single event effects on SB-CMOS will be of great benefit to many system designers (military and commercial alike) who require highly scaled, high-performance components with the capability to operate reliably in radiation laden environments. Furthermore, due to the outstanding performance of SB-CMOS for high-speed, low-power applications, SB-CMOS based integrated circuits have the ability to enable entirely new classes of consumer and commercial products and will likely find widespread adoption across the electronics industry.