SBIR Phase I: VCSELs On Silicon: CMOS Compatible Epitaxial Mesas On Large Silicon Wafers

This Small Business Innovation Research (SBIR) Phase I project proposes to develop a revolutionary, yet simple and well-designed technique for the cost effective deposition of compound semiconductor epitaxial material mesa arrays on large (300mm) silicon wafers. The subsequent processing steps integrate smoothly with silicon CMOS (Complementary Metal-Oxide-Semiconductor) processing similar to the current SiGe (Silicon Germanium) BiCMOS (Bipolar CMOS) technology. Previous attempts at the integration of III-V materials with silicon have had limited success due to many factors including high cost, CMOS incompatibility, small wafer size, and a lack of technological and market readiness. In contrast, the proposed solution is very cost effective, and it builds on recent technological progress in advanced materials deposition and handling. The vehicle chosen for the demonstration of this technology is the fabrication of high speed VCSEL (Vertical Cavity Surface Emitting Laser) arrays on silicon. The immediate application is in high speed interconnects for computer systems and peripherals including next generation USB (Universal Serial Bus) cables. The broader impact/commercial potential of this project lies in the following aspects: This technology can merge the advanced compound semiconductor materials with the superior processing and efficiency of silicon ICs. This will end years of isolated development and will bring new electronic and optoelectronic device capabilities to mainstream silicon processing. In electronics applications, high speed and high power transistors based on InP, and GaN device technologies will be processed with silicon CMOS on large wafers. This will integrate advanced analog and power functions with silicon CMOS based control and processing. In addition, it will offer an alternative route for the continuation of performance enhancement in silicon ICs independent of feature size reduction. In optoelectronics, the integration of GaAs and InP based optical emitters and receivers on silicon will allow the miniaturization and cost reduction of optical transmitter and receiver modules. The seamless integration of optical and electronic functions on silicon chips will lead to faster interconnects and will significantly reduce the cost per bit in fiber optic signal transmission.