SBIR/STTR Research Award

SBIR Phase I: A Novel Memory Having Both Volatile and Non-Volatile Modes For High Performance, Low Power Applications

Award identifier cc689913c9fff2da2198d653e8973f2b2544338a052a4ff71b6def054b9202e6Awarding agency National Science Foundation

Award amount

$150,000

Program and phase

SBIR · Phase I

Award year

2011

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
Zeno Semiconductor, Inc.
Proposal award date
2011-01-01
Contract end date
2011-12-31
UEI
FXE7MZ52LEN5
Solicitation number
Not reported
Topic code
IC

Research abstract

This Small Business Innovation Research (SBIR) Phase I project seeks to develop a novel memory, which has both volatile and non-volatile functionality. Such memory combines the non-volatile memory?s ability to retain information in the absence of power (such as Flash memory) and the fast access speed and reliability of a volatile memory (such as Static Random Access Memory (SRAM)). This memory is fabricated using a mainstream or near-production fabrication process and is a one-transistor device, which results in a compact cell size, suitable for cost-efficient high density applications. The proposed memory cell integrates a floating body transistor and a phase change memory element. During normal operation, the memory device functions as a floating body memory device and has SRAM-like performance, as in the access speed, power, and endurance capability. When power is removed from the memory device, the state of the floating body is saved into the phase change memory element by means of a mass, parallel, self-feedback mechanism. Subsequent to power restore, the original state of the floating body is recovered, also by means of a mass, parallel, self-feedback mechanism. The broader impact/commercial potential of this project is to enable power-efficient computing applications and mobile devices. For example, it can be used to reduce power consumptions in data centers. Data centers? annual energy consumption is estimated to be 150 billion kWh, about twice the capacity of the current US solar panel. A power-efficient memory such as the one proposed in this proposal can reduce the overall data centers? power consumption by up to 75%. Another application is to provide an integrated memory solution. Many electronic devices currently employ multiple types of memory, due to their own distinct characteristics. The proposed device will be able to combine the different types of memory into a single memory device.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

3 SBIR/STTR records share this UEI (2009–2012). Reported award amounts total $736,721. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Science Foundation

Agency intelligence

National Science Foundation

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