Software Defined Wideband DREX Receiver

To realize next generation missile defense radar systems with a significant improvement in performance requires more cost effective system implementations. Software defined radar (SDR) technologies together with field programmable gate array (FPGA) implementations promise reusable and low cost DREX multichannel receivers in smaller form factors. Real time firmware reconfiguration enables radar mode modifications in response to dynamic signal environments. To validate these capabilities and advantages, our team will investigate three advanced missile defense radar SDR benchmarks: 1) multichannel digital equalizers to compensate for manufacturing variances, 2) dynamically assignable channelized (DAC) filtering to enable spectral resource management and 3) multichannel independent phase dithering for system spur reduction. We will follow a modular, macro-based firmware development process that maximizes firmware maintenance and reuse. Our existing DREX prototyping testbed will be used to demonstrate the channelized SDR firmware. The innovative spur reduction processing incorporates novel SDR firmware into unique chip-level CMOS synthesizer hardware developed by our research partner. Application consistency is maintained through the use of ROSA open system interfaces. Our team’s unique background in missile defense radar research enables us to conduct hardware tradeoffs of SDR radar technology during Phase I to confirm the benefits of software defined radar technology.