Highly Integrated Silicon (Si)-based RF electronics

ATEI’s unique partnership with the University of Minnesota plans to exploits applied and fundamental research, respectively, to achieve unprecedented levels of integration for highly complex RF microwave, mm-wave and analog/digital/mixed-signal modules using Silicon Complementary Metal Oxide Semiconductor (CMOS) technology to support emerging DoD-critical applications such as wafer-scale phase array mono-static radars, bi-static radars, MIMO radars, direction finding (DF) signals intelligence(SIGINT), UAV Sense and avoid systems, RF seekers, Forward and side-looking fuse, low visibility precision landing sensor, highly-integrated electronic warfare systems, or compact sensing systems. In Phase I, ATEI and the University of Minnesota focused efforts on application research to establish key performance parameters such as phase noise, phase shifter resolution/accuracy, linear dynamic range, channel isolation, etc. and analyze the feasibility of the proposed integration scheme and RF/mixed signal circuits that will result in revolutionary capabilities or superior performance which cannot be achieved by current III-V technologies. Simulation and/or basic experiments, expected RF performance, integration level (RF and digital transistor counts), and required integration technologies (3D integration, etc.) of the proposed circuits was presented and discussed including proposed realistic fabrication technologies or necessary technology developments to realize the target RF/mixed signal circuits for the next phases. The results from our research proved the feasibility that highly integrated Si-based RF electronics and infrastructure to can be deployed in small form factor, low power and with superior capability and performance than modern phased-array and other traditional radars. In Phase II, ATEI and the University of Minnesota will design and test Silicon CMOS prototypes which would enable the realization of large-element or wafer scale MIMO radar. The principal blocks would involve the RF front-end for the receiver, the transmitter’s RF section and the MIMO DSP. The linearity of the RF blocks (especially those of the front-end) plays a critical role in determining the capacity of multi-target detection and resolution – the end-metric for any radar. The end-product of this work would be a single-chip CMOS design consisting of separate transmits and receive sections, each consisting of their respective RF and baseband sub-sections. Eventually, there has to be a central DSP which would run the MIMO algorithm on all the accumulated data, but some level of DSP, which can be done at the individual element level (like out-of-band filtering) would be integrated into the single CMOS chip. In phase II, digital-to-analog and analog-to digital conversions will be performed off-chip using test equipment. IF / baseband transmit waveforms and receive signal processing will be performed using a combination of algorithms develop in MATLAB and SIMULINK.