Next Generation Reconfigurable Field Programmable Gate Array

The MAESTRO Phase II SBIR’s focus is the design and build of a single board processor based on the MAESTRO chip developed by the U.S. Government. The board will be on a commercial VPX (Vita-46) 6U standard. The processor chip used on the board is a multi-core processor, with 49 identical processing cores, 4 banks of DDR2 memory, and 4 XAUI 10Gb interfaces. The VPX standard supports interfaces up to 40Gbps. The processor board will be designed as a prototype software development station for use by the MAESTRO community. The development includes an initial board support package, hardware and software documentation and porting of a software application from the phase I SBIR for validation of throughput. BENEFIT: The MAESTRO board has a number of applications, both terrestrial and space based. The initial prototype board will be used as a software development station for algorithmic development. The prototype board can be used as a verification vehicle for radiation testing and characterization of the MAESTRO processor itself. The board uses a powerful multi-core processor that has been developed using rad-hard by design libraries, and can be spun into a flight version for space applications.