SBIR/STTR Research Award

Radiation Fault Analysis for 45 Nanometer CMOS-SOI VLSI Circuits

Award identifier dc38721fd938bd065302a351e7e6d2c929bba3182ec98c6c24159d61256d027aAwarding agency Department of Defense · Defense Threat Reduction Agency

Award amount

$99,836

Program and phase

SBIR · Phase I

Award year

2010

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Award details

Awarding agency
Department of Defense
Branch
Defense Threat Reduction Agency
Recipient company
Lynguent, Inc.
Proposal award date
2010-02-18
Contract end date
2010-08-17
UEI
Not reported
Solicitation number
2009.2
Topic code
DTRA092-001

Research abstract

State of the art Radiation Hardened by Design (RHBD) techniques must scale down in feature size for radiation effects in 45 nm processes, and also scale up in complexity to support radiation fault analysis of VLSI circuits. Recent access to commercial 45 nm CMOS Silicon-on-Insulator (SOI) technologies has increased the interest in this technology for rad-hard electronic applications due to the inherent advantages for operation in radiation environments. However, the models that exist in the commercial design environments do not include the effects of radiation. Lynguent’s efficiency gains in compact model composition have enabled Vanderbilt-ISDE to transfer observed radiation effects from TCAD simulators into the commercial circuit simulators and correlate the results with measured data at the 90 nm process node. Applying Lynguent’s tools to a 45 nm CMOS SOI PDK is the logical next step in establishing radiation awareness at 45 nm. The outcome of this Phase 1 effort will be a fully featured BSIMSOI-CMX model and the definition of 45 nm Radiation Effects Library for use in the ModLyngTM Integrated Modeling Environment (IME). These Phase 1 results provide the platform for a Phase 2 implementation of high fidelity radiation fault analysis on 45 nm VLSI circuits and libraries.

Technology keywords

Not reported

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Agency intelligence

Department of Defense

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