Wideband DDS-based Programmable Frequency Synthesizer with Enhanced Phase-Noise and Spurious Free Dynamic Range Performance

This SBIR work plan consists of a research effort to explore and implement a three part innovation to achieve a wideband DDS-based programmable frequency synthesizer (PFS) with enhanced phase-noise and spurious free dynamic range (SFDR). The proposal summarizes the competitive advantages of various techniques for achieving PFS. This understanding provides the motivation for three innovations. Innovation (1) consists of a truncation-free DDS technique to achieve low phase-noise and high SFDR but sacrifices frequency resolution. Frequency resolution is recovered using Diophantine Frequency Synthesis (DFS), an approach initially developed for PLL-based systems that can also be applied to DDS architectures. The implementation embodies innovation (2) where DFS is used to program pairs of truncation-free DDS thereby recovering frequency resolution while preserving low phase noise. DFS uses frequency mixing and to maintain the desirable high SFDR, innovation (3) is realized where Diophantine Frequency Mixing Algorithms for suppressing mixing spurs and enhancing the SFDR are implemented. The research initiative consists of a theoretical and modeling effort combined with a hybrid circuit implementation and evaluation of the proposed PFS architecture to validate its efficacy. This effort will facilitate an integrated circuit implementation expected to achieve the desired performance goals and suitable for commercialization. BENEFIT: Agile frequency synthesis is fundamentally important to a vast range of military and commercial applications ranging from satellite communications to radars to navigation to scientific instrumentation. The proposed work plan will lay out the foundations of new frequency synthesis technology that can achieve multi-GHz frequency ranges with exceptional phase-noise (-150 dBc/Hz @ 1KHz) performance with very low spurious levels (SFDR>80dB) at the same while offering high frequency resolution (Hz) and very fast frequency hoping (ns). Phase – I of this proposed plan is focused on the theoretical modeling & optimization of the proposed high-level architectures as well as the discrete-component implementation of a prototype that will demonstrate the capacities of this new technology. Phase – II of this work plan will offer the opportunity of circuit integration. Miniaturization, ideally a single-chip frequency synthesizer of performance compatible with that promised by Phase - I effort, will enable the major advancement of several military and commercial applications. Successful demonstration of an integrated-circuit prototype is expected to attract significant attention in the RF & microwave community, especially from major semiconductor companies active in wireless communication products. Phase – III would allow refining this technology and embedding it in complex military and commercial systems.