Navy Applications of 4th Generation Deeply Coupled Computing Architectures

The objective is to investigate further the advantages of applying 4th generation deeply-coupled computing architectures and adaptive processing techniques to STAP. Specifically, we will explore building a STAP radar processor using this technology that has the appropriate format factor, throughput and capability to perform real-time, full degrees-of-freedom STAP processing on an airborne platform, starting with the E-2 Hawkeye. While Phase I concentrated on Doppler filtering, Phase II will include analysis of the entire STAP algorithm. This will be accomplished by: profiling the computational requirements of the full STAP algorithm using a single processor to understand and prioritize the major areas of opportunity for acceleration; evaluating partitioning schemes to reduce the computation time through parallel execution for the various routines, starting with the ones with the highest potential impact; completing an initial open, modular architecture of a QX4-based computer that will execute the STAP algorithm at appropriate real-time speeds using the SystemLab PS™ real-time platform simulator, optimizing the STAP algorithm, as needed, for the QX4 architecture, and benchmarking the QX4-based system against a single and quad X86 microprocessor-based system, including performance size, weight, power and cost metrics. The options will examine inserting this technology into the E-2 radar.