GENERAL PURPOSE READOUT CIRCUIT DESIGN WITH INTEGRATED DIGITAL PROCESSOR ARRAY

Eutecus proposes to develop scalable focal-plane sensor-processor array chips, 3D integrated with various sensors (e.g. InGaAs) sensitive in different IR spectral domains (e.g. NIR-SWIR). As opposed to the integrating type approaches, the sensor interface (read-out integrated circuit, ROIC) of the proposed design will contain precise resistive trans-impedance amplifiers (RTIAs) and fast analog-to-digital (AD) converters tightly coupled to a digital processor array, which will allow very high temporal sampling rates combined with near sensor algorithmic calculations. The proposed device will be able to handle input frequencies up to the megahertz (MHz) range. The processors will be equipped with local data memory per pixel, a multiple-add type arithmetic unit, a special statistical unit, and a morphological unit. The proposed sensor-processor chip will be able to perform Fourier analysis or calculate other computationally intensive linear (e.g. mean, convolution), non-linear (e.g. min, max, median) or binary (mathematical morphology) operations, and provide the processed output at a speed of few thousand frames per second. The output can be either an image and/or a decision, being able to trigger instantaneously the main processor of the host system when a certain object / target or a special visual event (identified through its space-time-spectral signature) occurs.