Optimizing and Mapping Tool Chain for FPGA Programming

Field Programmable Gate Arrays (FPGAs) are an important technology for many DoD and commercial high performance computing applications. A number of supercomputing, workstation, and embedded computing hardware platforms have emerged recently to supply FPGA computing power for these applications. Unfortunately, developing for these platforms is currently a long, difficult and error-prone process. While a number of commercial software tools are emerging to facilitate programming beyond VHDL, the high-level application mapping problem to heterogeneous complexes of general purpose processors and FPGAs is still a complex manual programming task. In this Phase II SBIR project, we will modify the R-Stream® high-level compiler to automatically map programs expressed in C to such heterogeneous complexes. This technology will be applicable to a range of system targets including supercomputers, workstations, and high performance embedded computing systems. R-Stream will emit mapped programs in a “lower-level” language that is used to express computations to be performed on individual FPGAs, as well as the choreography of computation among these devices. Our Phase I project established the feasibility of extending R-Stream for this purpose. The benefit of this project is that it will improve productivity, portability of programming systems employing FPGAs, as well as improved quality of the mappings that are achieved.