Hardware Accelerated Super Resolution for MDA Interceptors

MDA is currently developing advanced interceptors for its BMDS. Imaging technology is crucial to this effort for several purposes, including navigation, false-alarm/decoy identification, and estimation of position and speed of potential targets. Although high-resolution imaging systems are readily available, these require (1) power-hungry CMOS arrays (or FPAs) and (2) large-aperture optics, which are heavy, expensive and may not be compatible with the aerodynamic profile of high-speed interceptors. Fortunately, signal processing methods have been developed that enable high-resolution image-capture using low-resolution equipment exclusively, a family of algorithms know as super-resolution. Although super-resolution algorithms have been studied extensively by the research community, their implementation and deployment have been limited due to high computational cost and the inability to work in real-time in realistic applications. We propose the acceleration of super resolution routines using readily available hardware; in particular, an FPGA platform will be utilized given its compatibility with the power/size/cost requirements of missile interceptors.