Using Next Generation Processors

The goal of this proposal is to provide better understanding and improve utilization of next generation computational resources for compute intensive systems. In practical terms, this translates to delivering tools to assist in selecting the most appropriate multi-core processor for different target compute problems and applying the appropriate optimizations. Due to the issues of increasing power (power wall), long memory latency (memory wall), and diminishing returns on exploiting instruction level parallelism (ILP wall), the doubling of uniprocessor performance has slowed from 18 months to 5 years. Instead of increasing clock frequency, the current primary method of increasing processor performance is to increase parallelism. Fortunately, Moore's law continues to provide more transistors per chip. All these factors point to the continued scaling of chip multi-processing into the future, where multiple processor cores are placed on-die. The chip multiprocessor (CMP) design space encompasses a wide variety of designs such as small scale homogeneous designs (desktop CPUs), heterogeneous designs (Cell), many-core application specic designs (GPU, PPU, ClearSpeed, SPI), and many-core general purpose designs (Larrabee and Tilera). This shift to multi-core processors comes with new challenges. The wide variety of designs utilizes different ISAs, memory models, programming models, and architectures. Different programming techniques and optimization strategies are required to optimize performance for the same problem across the spectrum of designs. Furthermore, the same application may require multiple implementations in order to compare across different architectures. The challenge from a system design point of view is to select the “optimal” processor design/s for each target problem and apply the appropriate software or system optimizations. One solution is to categorize high performance problems, the CMP architectures, and the available optimization techniques. Then, use this information to obtain optimal mapping of target workload to processor for system design.