Asynchronous Techniques for Ultra-Low-Power Radiation-Hard Electronics

The design of an asynchronous MIPS microprocessor and of an asynchronous 8051 microcontroller (both developed in the proposer's laboratory) have demonstrated that asynchronous techniques, in particular quasi-delay-insensitive (QDI) techniques, can produce circuits with high throughput and low power consumption. Furthermore, the absence of almost all delay assumptions in QDI design results in a remarkable robustness to parameter variations which has been observed both through simulation and in testing of actual chips. A novel approach to make QDI circuits entirely tolerant to soft errors is proposed. The method does not rely on any particular fabrication technique---standard CMOS process (bulk or SOI) is used---and does not use TMR. The correction of a soft error is entirely done at the logic level. Several soft errors can be simultaneously corrected provided they do not happen too close to each other in space and time. The first objective of this project is to develop and test prototypes soft-error tolerant microcontroller, memories, and FPGAs based on this approach. The second objective is to select and specify a first design for commercialization.